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Scalable, Efficient Deep Learning.

Data is everywhere and growing at an alarming rate. We are building machines inspired by the brain to make data actionable for enterprise customers.

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About Us

Machine learning at massive scale. Simplified.

Founded by experts in machine learning, neuroscience, processor architecture, and chip design, Nervana Systems is bringing unprecedented scale and simplicity to the application of brain-inspired algorithms. Deep learning has emerged as the leading strategy for making sense of a wide variety of data but is very computationally intensive. We are developing a scalable hardware solution to solve these types of problems. By making unsupervised learning dramatically faster and more scalable, customers at all levels can derive meaningful insights from their data, an ability previously available only to companies with massively large computing infrastructures.

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News

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OUR TEAM

Naveen Rao, PhD

CEO and Co-founder

BSEE (computer science and EE), Duke University
PhD (neuroscience), Brown University

Naveen brings a unique perspective to Nervana Systems being at the intersection of semiconductor design, machine learning, and computational neuroscience for the past 17 years. He’s a Silicon Valley veteran having spent 12 years at a number of venture-backed startups, spanning the microprocessor, networking, wireless, and video compression spaces. He successfully taped-out multiple complex chips, managed and designed FPGA-based products, and developed algorithms for video compression, wireless, and networking. Naveen started his career at Sun Microsystems working on UltraSparc processors. From there he went on to TeraGen, Caly Networks, Kealia, and W&W Communications. Most recently, Naveen was part of Qualcomm’s neuromorphic research group investigating artificial neural computation. In his graduate work, Naveen combined his engineering background with neuroscience to explore the neural mechanisms of computation underlying motor planning for neural prosthetic applications in the lab of Dr. John Donoghue.

Amir Khosrowshahi, PhD

CTO and Co-founder

AB (physics and math), Harvard University
AM (physics), Harvard University
PhD (computational neuroscience), UC Berkeley

Amir has a diverse business and research background. He recently led the neuromorphic analog VLSI sensor effort at Qualcomm. Previously, he was consultant to successful startups including Xl2Web (now Google Spreadsheets) and Tellme Networks (acquired by Microsoft). Prior to this, he was a VP at Goldman Sachs, leading a derivatives business, with other roles in principal investment, capital markets, M&A, portfolio trading, and structured finance. His PhD thesis work, advised by Bruno Olshausen, was on large-scale unsupervised learning algorithms. His research experience includes experimental neuroscience, computer vision, parallel computing, and machine learning on clusters and GPUs.

Arjun Bansal, PhD

VP of Algorithms and Co-founder

BS with honors (computer science), Caltech
PhD (neuroscience), Brown University
Postdoc (opthalmology & neurosurgery), Harvard Medical School & BCH

Arjun has over 12 years of research experience spanning computational neuroscience and brain-machine interfaces along with stints in industry as a venture capitalist at Slater Fund, and as a software engineer at Microsoft. He was most recently working on deep learning for speech recognition and motor control. Arjun was the lead author on four peer-reviewed publications applying machine learning and signal processing techniques to big data problems in neuroscience. He did postdoctoral work at Harvard Medical School & Boston Children’s Hospital (2011-13) in the neurosurgery department analyzing large-scale neurophysiological data from epilepsy patients to understand the neural basis of human object recognition and learning and memory.

Carey Kloss

VP of Hardware

BS (computer engineering), Carnegie Mellon University
MS (computer architecture), Carnegie Mellon University

Carey has 18 years of experience in ASIC development at a variety of venture backed startups and public companies including Intel and Cisco. His projects have spanned a wide range of technologies from high end CPU architecture to low-power enterprise-grade packet processing. Most recently he was a Sr. Director at Aquantia Corporation where he managed both the Verification and Program Management activities of Aquantia’s cutting edge mixed-signal ASIC development. Carey is a recognized expert in ASIC verification, serving as a panelist at DAC, DVCon, and Verisity’s Club Verification conferences. His work in assertion-based random verification resulted in a Best Paper award at DVCon 2004, and he is currently a member of the DAC Designer Track program committee for 2014.

Andrew Yang

Senior Director of Hardware

BSE (electrical engineering), Princeton University
MS (electrical engineering), Stanford University

Andrew has more than 15 years of experience in semiconductor development and design at a variety of venture-backed startups and public companies including AMD, Sun Microsystems, and Cavium. He has successfully taped out multiple projects in areas ranging from high-end enterprise to consumer-grade equipment for applications in networking, computing, video compression, and video distribution. These projects have included analog/mixed-signal full custom IC design, ASIC, and FPGA-based products. Andrew was a Director at Cavium where he managed the ASIC design team and back-end implementation of Cavium’s consumer wireless video processor products.

Urs Köster, PhD

Senior Algorithms Engineer

MSci (physics with photonics), St Andrews University
PhD (computer science), Helsinki University
Postdoc (neuroscience), UC Berkeley

Urs has over 9 years of research experience in machine learning, spanning areas from computer vision and image processing to large scale neural data analysis. During his PhD with Aapo Hyvärinen, Urs developed unsupervised learning algorithms inspired by Independent Component Analysis for natural images, with applications in image processing, and linking the learned models to representations in the brain. For his postdoctoral work, advised by Bruno Olshausen, he recorded large scale electrophysiology data from the visual system and applied learning algorithms such as Restricted Boltzmann Machines to understand the circuit mechanisms of mammalian vision.

Anil Thomas

Principal Data Scientist

BTech (computer engineering), NITK, India
MS (computer science), University of Illinois at Urbana-Champaign

Anil is a Kaggle champion (top rank #2) where he has applied his machine learning expertise to enterprise datasets, achieving near human level performance in some cases. He brings with him two decades of experience in the software industry. As a hands-on data scientist, he has experience building predictive models for business applications such as customer retention and demand forecasting. He is passionate about working with data, sourced from disparate domains. During his long tenure at Cisco Systems, he helped with bootstrapping a new business unit and led engineering teams that spanned multiple sites. Anil's collaborations with other innovators at Cisco led to many patents.

Prashant Arora

Principal Hardware Engineer

BTech (computer science and engineering), IIT Delhi
MS (information and computer science), UC Irvine

Prashant has 15 years of experience in semiconductor development at Broadcom, Cavium, Cisco and venture-backed startups. His projects have ranged from high-performance switching and routing ASICs for enterprise applications to low-power video processors for consumer products. Prashant has a wide breadth of experience in ASIC/FPGA design, verification and back-end flows. His interests and contributions have extended to low-level software development, including device drivers and embedded systems programming.

Scott Leishman

Principal Data Scientist

BSc (computer science), University of Toronto
MSc (computer science), University of Toronto

Scott has over nine years experience creating machine learning based solutions to solve large-scale, real-world problems. At CoreLogic, he led model development and support of FraudMark UK, an award-winning mortgage fraud detection system that currently processes one out of every three residential loans (circa £2 billion in originations each month). Scott has contributed models, analysis and software to support automated house price valuation, securitized asset rating, and credit card fraud detection. He's had multiple top ten finishes in the KDD Cup and Kaggle competitions on tasks ranging from author disambiguation to music preference rating. Scott is a former member of the Machine Learning group at the University of Toronto. Supervised by Sam Roweis, his research focused on ways to improve optical character recognition by exploiting contextual and language-based cues.

Alex Park, PhD

Staff Algorithms Engineer

BS (mathematics), MIT
BS (electrical engineering and computer science), MIT
MEng (electrical engineering and computer science), MIT
PhD (electrical engineering and computer science), MIT

Alex has 12 years of experience in machine learning and quantitative modeling both in research and industry. While at MIT, he worked on a variety of topics related to speech and audio processing, including automatic speech recognition, speaker identification, multimodal biometrics, noise robust recognition, auditory signal processing, and unsupervised learning on raw audio data. His doctoral research, advised by Dr. James Glass, focused on the problem of word acquisition from unlabeled data. After MIT, Alex joined Tower Research Capital as a quantitative trader, where he developed automated algorithms for modeling and trading equities.

Brian Cheung

Deep Learning Researcher

BSE (electrical engineering), Cooper Union
MS (electrical engineering), Cooper Union
PhD candidate (vision science), UC Berkeley

Brian has a wide breadth of experience in computer vision, machine learning, and robotics. Most recently, he has been developing unsupervised learning algorithms for natural images and studying the correspondence between Deep Learning models and neural data. His research projects have included using convolutional neural networks for face detection, convex optimization techniques for fitting parametric models, heterogenous sensor networks, and autonomous collaboration and maze navigation using multiple robots. Brian has extensive background in designing software for machine learning and deep learning.

Luke Hornof, PhD

Principal Software Engineer

BS (computer engineering), Carnegie Mellon University
PhD (computer science), University of Rennes, France
Postdoc (computer science), University of Pennsylvania

Luke has over 14 years of experience in a variety of software engineering roles at successful startups as well as semiconductor companies such as Sun Microsystems and Transmeta. His projects have included building the world's first hardware implementation of the AMD-64 instruction set, large-scale web infrastructures, and Big Data predictive engines for real-time advertisement placement. His research work on program analyses and optimizations for fast run-time code generation resulted in over a dozen peer-reviewed publications, and he was recently a technical editor for a book on real-time analytics.

Jesse Livezey

Deep Learning Researcher

BA (physics and mathematics), Cornell University
MA (physics), UC Berkeley
PhD candidate (physics), UC Berkeley

Jesse has experience creating mathematical models for complex systems ranging from electron clouds in particle accelerators to networks of interacting neurons. Recently, he has been applying deep learning models to sensory signals and developing tools for the analysis of model properties. His research interests include how the brain develops hierarchical models of the world around us and how these ideas can be replicated in software. His research projects have included spiking models of the visual cortex, generative probabilistic models of signals, and sensory motor control loops.

Tony Werner, PhD

Principal Hardware Engineer

BS (computer engineering), University of Illinois at Urbana-Champaign
MS (electrical engineering), University of Arizona
PhD (electrical engineering), UC Davis

Tony is a published expert in ASIC design and brings 17 years of experience from Hitachi, ATI, Cisco, and multiple venture-backed startups. His projects have ranged from embedded processor architectures to high-performance switching and routing ASICs for enterprise applications.

Jeff DelChiaro

Principal Hardware Engineer

BS (electrical engineering), San Jose State University

Jeff has 20 years of experience doing ASIC development in fault-tolerant computing and networking. Projects ranged from redundant and fault tolerant enterprise storage to high end switching and routing products. Most recently as a Technical Leader at Cisco, he lead the verification of enterprise grade ethernet switching 28nm ASICs and SoCs.

Jessica Rosenthal

Operations Assistant

BA (psychology), USC

Jessica is a recent graduate from the University of Southern California, with a degree in Psychology with a business emphasis. Her studies were focused on the nature of interpersonal relations, consumer behavior, and market research. Prior to managing the operation efforts at Nervana Systems, Jessica played several administrative roles as a division coordinator, legal administrator, and assistant to high-level executives.

Scott Gray

Principal Software Engineer

BS (physics and computer science), University of Illinois at Urbana-Champaign

Scott brings over 15 years of experience in software engineering and web infrastructure at a variety of startups and larger companies. His hobbies include computational neuroscience and designing artificial intelligence algorithms for the game of Go. Most recently, he reverse engineered the NVidia Maxwell architecture using a custom built assembler to achieve state-of-the-art performance in numerical linear algebra.

Horace Lau

Principal Hardware Engineer

BS (computer engineering/computer science), Carnegie Mellon University
MS (computer engineering), Carnegie Mellon University

Horace has over 17 years of experience in the semiconductor industry with Silicon Valley brands like Silicon Graphics (SGI), MIPS and Broadcom. He has been a significant contributor to successful products ranging from high performance embedded processors to multi-terabit ethernet switches.

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ADVISORS

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investors

DFJ
VC, Menlo Park
Allen & Co.
Investment bank, New York
AME Cloud Ventures
Early stage fund of Jerry Yang
Fuel Capital
Early stage venture fund, San Francisco
Sam Altman
President of Y Combinator
SV Angel
San Francisco-based angel firm
Eric Baker
Co-founder of StubHub, founder and CEO of Viagogo
Scott Banister
Co-founder and CTO of IronPort
Dara Khosrowshahi
CEO of Expedia
Owen van Natta
Former COO of Facebook, former CEO of Myspace
Ali & Hadi Partovi
Co-founders of iLike, LinkExchange, Tellme, and currently of Code.org
Geoff Ralston
Partner at Y Combinator
Aditya Agarwal & Ruchi Sanghvi
Co-founders of Cove, currently VP of Engineering at Dropbox
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CONTACT

WE ARE HIRING!

If you are passionate about hardware and machine learning, send us your resume at jobs@nervanasys.com.

We have offices in San Diego and Mountain View.

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